In the fabrication of semiconductor devices, it is often necessary to provide a long diffused regions such as those used as bitlines in memory devices. It is desirable that the bitline have the lowest possible sheet resistance, since decreasing resistance of the bitline will increase the speed of the device. Further, the number of contacts made to the bitline depends upon the sheet resistance; a lower sheet resistance requires less contacts. Using today's technology, one contact is made per every ten cells along a bitline.
Prior art buried bitlines are formed in a process where a pad oxide layer and a nitride layer are patterned and etched to expose the area in which a diffused region is desired. A suitable dopant is implanted into the exposed region and a subsequent anneal process diffuses the dopant. As the diffused regions are annealed, a self-aligned field oxide is grown over the diffused regions. The sheet resistance of a prior art buried bitline will, to a large degree, correspond to the width of the bitline. While a low sheet resistance is desirable, this desire must be balanced with the need for reducing the size of the devices to increase density.
One way of reducing the sheet resistance of a diffused region is to provide a metal alloy such as titanium silicide (TiSi.sub.2) or tungsten silicide (WSi.sub.2) along the upper surface of the bitline. While the silicide bitlines have considerably less resistance, it is still desirable to reduce their width even further.
Therefore, a need has arisen in the industry to provide a buried diffused region with low sheet resistance.